Optical packet interconnection networks provide possible solutions for interchip communications bottleneck, especially, in high-performance computing systems (HPCS). However, the main challenge in the design of next-generation HPCS is the communication between processors and memory elements which are not able to address the latency, scalability, and through-put requirements.
Contemporary processors are capable of working at giga-floating-point operations per second (GFLOPS), and high-speed memory elements can be written and read at data rates of hundreds of gigabits per second. It is well recognized that the performance bottleneck is shifting towards the data exchange medium between processors and memory elements in multi-processor systems. Increasing the pin count of electronic integrated circuits is becoming more demanding, while growing data rates lead to increased power consumption of communication chips and greater difficulty in transmitting high-speed electronic signals over distances of tens of meters. These factors clearly render future electronic interconnection networks complex to design and expensive to manufacture. Fiber-optic technology offers a preferable transmission medium for multiprocessor HPCS interconnects. Optical packet switching fabrics provides high performance characteristics necessary for efficient communications between supercomputer processor, memory and storage elements.
The data vortex is one optical packet network designed specifically for large-scale processor-memory interconnections. Most large-scale optical packet switches include the data vortex, share the semiconductor optical amplifier (SOA) as the central active optical switch component. Semiconductor optical amplifiers (SOAs) offer substantial gain, low latency, and relatively uniform gain. They have, therefore, been utilized as switching gates in optical packet switching (OPS) networks. It has been shown that wavelength division multiplexing (WDM) optical packets can be transmitted through many SOAs while maintaining sufficient signal integrity.
Data Vortex Switching Node
The node structure has two input ports and two output ports. At each input port, a small portion of optical power is tapped off by a coupler to decode the header and frame information. The payload data is transparent and switched by the SOAs. The header and frame bits are converted into electronic signals and, along with the electronic input control signal from the inner cylinder node, are processed in the node control board. Accordingly, driving signals are generated to switch the SOAs on or off. In the meantime, a control signal to the outer cylinder is also generated. The total latency, from the input port to output port, is approximately 4.3 ns.
“A fully implemented 12×12 Data Vortex Optical Packet Switching Interconnection Network” published paper in Journal of Lightwave Technology Vol. 23, October 2005, provides a fully implemented data vortex OPS interconnection network. It demonstrates complete packet routing functionality from 12 input ports to 12 output ports for data packet containing eight payload wavelengths modulated at 10 Gb/s each, with median latencies of approximately 115 ns, while maintaining a bit error rate (BER) of 10−12 or better.
However, it is a cumbersome process to implement multi-stage data vortex network and its associated hardware for high performance computing requirements. Data Vortex (DV) is essentially a synchronous unidirectional switch with packets moving in the forward direction. It provides data flow only in one direction. In order to have a bidirectional operation with DV switch, one will require two data vortex interconnection networks connected in parallel, for both forward and reverse operations. Generally, the optical devices are bi-directional so as to increase the throughput and utilize the channel capacity but when implemented with uni-directional data vortexs (DVs) the number of nodes and other optical components are doubled, thereby, reducing the overall throughput of the system.
FIG. 1 discloses one such bidirectional data vortex (BDV) setup by means of two data vortex interconnection networks connected in parallel. Each node has to be duplicated for bidirectional operation. Each node acts as a bidirectional node by connecting 1×2/2×1 switches outside the node setup. A control unit outside the node is required to control the forward and reverse directional operation of 1×2/2×1 switch. The switches and control unit at each node is adequate because DV switch provides a distributed control switch and not centrally controlled switch. Also extra fibers are required to connect the SOA switches and 1×2/2×1 switches connected outside the node. However, there is not much improvement in the BER characteristics, throughput latency, fault tolerance and reliability of this BDV switch.
Therefore, there is a need to develop efficient bidirectional Data Vortex architecture with bidirectional links in which the packets are routed both in the forward as well as in the reverse directions.